Integrated circuit (IC) designers commonly describe their designs in HDL (hardware description language) such as Verilog, VHDL, SystemC, and the like. In IC design, hardware emulation may refer to the process of replicating the behavior of one or more pieces of hardware (typically a design under test) with another piece of hardware, typically a special-purpose emulation system. An emulation model is usually based on a hardware description language source code, which is compiled into the format used by emulation system. The goal is debugging and functional verification of the system being designed. Overall progress of the emulation is usually controlled by a clock signal generated on the emulator hardware.
There are a number of clock modeling styles in HDL languages that define non-periodic clocks, often with pseudo-random order of edge events between different clock signals. The intent of such generators is to model the behavior of the clock generators that are hardware devices or hardware macros of application specific integrated circuits (ASICs), such as phase locked loops (PLLs). In general, these behavioral generators are not HDL synthesizable code. Those generators usually expose design bugs when crossing different clock domains for designs that have asynchronous clock domains that are derived from independent oscillators. As a result, order of clocking events may not be deterministic in physical hardware for such designs.
The clocking system defined with the above described behavioral code can be distributed in the system, which can cause performance issues. In general, maintaining consistent delays among different FPGAs in an emulation system may be difficult.